1. Field of the Invention
The present invention relates to a semiconductor device in which DRAMs and SRAMs are combined. It particularly relates to a semiconductor device having a structure in which a shared contact that is effective for reducing a cell area of SRAMs can be easily formed, and to a method of manufacturing the device.
2. Description of the Prior Art
FIG. 9 is a circuit diagram showing the memory cell of a SRAM used in a conventional semiconductor device. Referring to FIG. 9, PMOS load transistors 101 and 102 each serve as a load, NMOS drive transistors 103 and 104 each serve as a charge puller, NMOS access transistors 105 and 106 each serve as an information deriver to a bit line, Vcc is a power supply line, GND is a grand line, and WL is a word line. In addition, NMOS access transistor 105 connects with bit line xe2x80x98BLxe2x80x99, and NMOS access transistor 106 connects with bit bar line xe2x80x98/BLxe2x80x99.
FIG. 10 is a layout diagram showing the memory cell of a SRAM used in a conventional semiconductor device, and it is a layout sample of the circuit diagram shown in FIG. 9. In FIG. 10, because the same or corresponding part is designated by the same numeral as the one in FIG. 9, the explanation is omitted. Gate 111 is the gate of PMOS load transistor 101 and NMOS drive transistor 103, gate 112 is the gate of PMOS load transistor 102 and NMOS drive transistor 104, gate 113 is the gate of NMOS access transistor 105, and gate 114 is the gate of NMOS access transistor 106.
Additionally, in FIG. 10, on-the-active-region contact 115 is the on-the-active-region contact of NMOS drive transistor 103 and NMOS access transistor 105, on-the-gate contact 116 is the on-the-gate contact of PMOS load transistor 102 and NMOS drive transistor 104, on-the-active-region contact 117 is the on-the-active-region contact of PMOS load transistor 101, on-the-active-region contact 118 is the on-the-active-region contact of PMOS load transistor 102, on-the-gate contact 119 is the on-the-gate contact of PMOS load transistor 101 and NMOS drive transistor 103, on-the-active-region contact 120 is the on-the-active-region contact of NMOS drive transistor 104 and NMOS access transistor 106, first layer aluminum wiring 121 connects on-the-active-region contacts 115, 117, and on-the-gate contact 116, first layer aluminum wiring 122 connects on-the-active-region contacts 118,120 and on-the-gate contact 119, first layer aluminum wiring 123 connects with PMOS load transistor 101, on-the-active-region contact 124 is the on-the-active-region contact of PMOS load transistor 102, and first layer aluminum wiring 125 connects with on-the-active-region contact 124.
Additionally, first layer aluminum wiring 121 is the cross coupling part that connects the output of PMOS load transistor 101 and NMOS drive transistor 103 to gate 112 of PMOS load transistor 102 and NMOS drive transistor 104, and first layer aluminum wiring 122 is the cross coupling part that connects the output of PMOS load transistor 102 and NMOS drive transistor 104 to gate 111 of PMOS load transistor 101 and NMOS drive transistor 103. Through-holes and aluminum wirings existing above the first layer aluminum wiring are not shown. In the layout sample shown in FIG. 10, contacts 115-120, and 124 are independently arranged. Herein, contacts 115-120, and 124 independently arranged are occasionally referred to as xe2x80x9cusual contactxe2x80x9d.
FIG. 11 is a layout diagram showing the memory cell of a SRAM used in the conventional semiconductor device, and it is a sample of the reduction of the cell region by use of a shared contact in comparison to the layout diagram shown in FIG. 10. Because in FIG. 11 the same numerals show the same or equivalent parts to the ones in FIG. 10, the explanation is omitted. Shared contact 131 forms on-the-gate contact 116 and on-the-active-region contact 117 by use of one contact, and shared contact 132 forms on-the-gate contact 119 and on-the-active-region contact 118 by use of a simple contact. As shown in FIG. 11, because the cell size in the direction of the gate width is reduced, the cell region of the SRAM can be reduced.
FIG. 12 is a sectional view showing the manufacturing process of a SRAM in the conventional semiconductor device, and it corresponds to the sectional view along the line A-Axe2x80x2 shown in FIG. 11. In FIG. 12, well 201 is present within the silicon substrate; isolation oxide film 202 and gate oxide film 203 are formed on well 201; gate electrode 204 is equivalent to gate 112; gate wiring 205 is equivalent to the wiring part of gate 111; side wall 206 is formed over the sidewall of gate electrode 204; side wall 207 is formed over the sidewall of gate electrode 205; diffused layer 208 is the diffused layer of source/drain; silicide layer 209 is a silicide layer over diffused layer 208; silicide layer 210 is a silicide layer over gate electrode 204; silicide layer 211 is a silicide layer over gate wiring 205; and silicon nitride film 212 is formed over isolation oxide film 202.
Moreover, in FIG. 12, contact interlayer film 213 is formed with silicon dioxide film; barrier metals 214 and 215 each are formed over the bottom and the sidewall of the contact; tungsten plugs 216 and 217 (referred to as W plug hereinafter) each are formed within the contact holes; barrier metals 218 and 219 are respectively formed over the bottom of aluminum wirings 220 and 221; and ARC (Anti Reflective Coat) films 222 and 223 are formed as an anti-reflecting film in a photolithography process. Here, on-the-active-region contact 124 corresponds to the area where barrier metal 214 and W plug 216 are formed; shared contact 132 corresponds to the area where barrier metal 215 and W plug 217 are formed; first layer aluminum wiring 122 corresponds to the area where barrier metal 218, aluminum wiring 220, and ARC film 222 are formed; and first layer aluminum wiring 125 corresponds to the area where barrier metal 219, aluminum wiring 221, and A RC film 223 are formed. On-the-active-region contact 124 and shared contact 132 are formed in the same process, and they are not formed in different processes, for instance, a photolithography process and an etching process. Incidentally, although not shown in the sectional view, contacts existing on gates 113 and 114 are also formed in the same process as the process in which on-the-active-region contact 124 and shared contact 132 are formed.
Examples of the patent disclosing the conventional semiconductor device described above include Japanese Patent No. 3,064,999 and U.S. Pat. No. 6,031,271.
The conventional semiconductor device has been constructed as mentioned above. As a result, because in a system LSI in which DRAMs and SRAMs are combined, a contact interlayer film is thicker in order to form the capacitor layer of the DRAM, there exist a drawback that forming a usual or typical contact and a shared contact at the same time is difficult; the failure of junction leakage occurs; and the contact resistance increases.
The drawback of the conventional technology will next be described in detail.
In the process of manufacturing the SRAM of the conventional semiconductor device shown in FIG. 12, since the film thickness of contact interlayer film 213 is 0.5-0.8 xcexcm, on-the-active-region contact 124 and shared contact 132 can be formed at the same time. On the other hand, in the manufacturing process of a system LSI in which DRAMs and SRAMs are combined, because the film thickness of contact interlayer film 213 should be 1.0-3.0 xcexcm in order to form the capacitor layer of the DRAM, the simultaneous formation of on-the-active-region contact 124 and shared contact 132 becomes difficult.
Additionally, in FIG. 12, when on-the-active-region contact 124 and shared contact 132 are formed by etching contact interlayer film 213 formed with silicon dioxide film by use of, for instance, a dry etching method, silicon nitride film 212 has the function of stopping the etching of contact interlayer film 213 by means of a selective etching method in which a difference in etching rate is used. That is, silicon nitride film 212 serves as a stopper layer in the etching process. However, the part of silicon nitride film 212 deposited over side wall 207 has a lower selective ratio to the silicon dioxide film than the part of silicon nitride film 212 deposited over the flat area. Furthermore, because, when the film thickness of contact interlayer film 213 is large, an over-etching time becomes long in the etching process in which shared contact 132 is formed, the part of silicon nitride film 212 deposited over side wall 207 is almost removed. In addition, side wall 207 (formed with silicon nitride film) is almost removed in the etching process of silicon nitride film 212 following the etching process of contact interlayer film 213.
For this reason, W plug 217 and barrier metal 215 of shared contact 132 will electrically connect with side wall 207 between silicide layer 209 and gate wiring 205. Because the diffused layer in this area has a low dopant concentration due to the LDD structure, and therefore has hardly undergone a silicide formation reaction, there is a drawback that these affairs cause a failure of junction leakage. Moreover, in an etching process in which on-the-active-region contact 124 and shared contact 132 are formed within contact interlayer film 213, when the etching is done in the etching condition where the selective ratio to silicon nitride film 212 is increased, on-the-active-region contact 124 and shared contact 132 have a taper angle lower than 90xc2x0, and form an extreme gentle-slope taper. Therefore, since the diameters at the bottoms of contacts 124 and 132 is smaller when the film thickness of contact interlayer film 213 is larger, there has been a drawback that the contact resistance increases; furthermore there occurs a failure that on-the-active-region contact 124 and shared contact 132 have no opening.
The present invention has been accomplished to solve the above-mentioned problem. An object of the present invention is to provide a semiconductor device where, in a system LSI in which DRAMs and SRAMs are combined, a usual contact and a shared contact can be formed at the same time, and the occurrence of the junction leakage failure and the increase in the contact resistance can be suppressed even when the film thickness of a contact interlayer film becomes large so as to form the capacitor layer of the DRAM, and to provide the manufacturing method thereof.
According to a first aspect of the present invention, there is provided a semiconductor device in which DRAMs and SRAMs are combined, the device comprising in the SRAM region: a first silicide layer formed on the surface of a diffused layer adjacent to a gate electrode; a second silicide layer on the surface of the gate electrode; an insulating side wall formed over the sidewall of the gate electrode; a first contact hole opened in a first interlayer dielectric formed on top, and exposing the side wall and the first and second silicide layers in the hole; a first contact which constitutes a shared contact between the first and second silicide layers through a first plug within the first contact hole; a second contact hole opened in a second interlayer dielectric formed on top; a first wiring layer formed on this second interlayer dielectric; a second contact for connecting electrically the first contact to the first wiring layer through a second plug within the second contact hole; a third contact hole opened in the first and second interlayer dielectrics, and exposing the first silicide layer on the surface of the diffused layer in the hole; and a third contact for connecting electrically the first silicide layer to the first wiring layer through the second plug within the third contact hole.
Here, the third contact formed in the third contact hole may have the first plug between the second plug and the first silicide on the surface of the diffused layer.
The semiconductor device further comprises in the DRAM region: an insulating side wall over the sidewall of a gate electrode; a lower contact formed through the first plug within the first contact hole which is opened in the first interlayer dielectric formed on top, adjacent to the gate electrode, and exposes the surface of the diffused layer; and an upper contact formed through the second plug within the second contact hole opened in the second interlayer dielectric formed on top, and connecting electrically the lower contact to the first wiring layer.
The first contact may be formed in the same process as the lower contact of the DRAM.
The second and third contacts may be formed in the same process as the upper contact of the DRAM.
At least one of the first and second plugs may be made of a metal containing tungsten.
The second interlayer dielectric may be constituted by stacking a second dielectric on a first dielectric, and the second contact hole may be opened by selective etching between the first and second dielectrics.
The first and second dielectrics may be respectively constituted by silicon nitride and silicon oxide.
According to a second aspect of the present invention, there is a method of manufacturing a semiconductor device in which DRAMs and SRAMs are combined, comprising the steps of: forming a insulating side wall over the sidewall of a gate electrode; converting the surface of a diffused layer and the surface of the gate electrode into silicide; forming a first interlayer dielectric; forming the opening of a lower contact of the DRAM and the opening of a first contact of the SRAM in the first interlayer dielectric; forming first plugs within the opening of the lower contact of the DRAM and the opening of the first contact of the SRAM; forming a dielectric for selective-etching over the DRAM; forming a capacitor layer over the DRAM while forming a second interlayer dielectric over the SRAM; forming the opening of an upper contact of the DRAM, the opening of a second contact of the SRAM, and the opening of a third contact of the SRAM; and forming second plugs within the opening of the upper contact of the DRAM, the opening of the second contact of the SRAM, and the opening of the third contact of the SRAM.
Here, the first plug may be formed in the opening of the lower contact of the DRAM, and in a region which constitutes a shared contact among the openings of the first contact of the SRAM.